The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field.
Most of the liquid crystal displays on the present market are backlight type liquid crystal displays, which comprise a liquid crystal display panel and a backlight module. The working principle of the liquid crystal display panel is that the Liquid Crystal is injected between the Thin Film Transistor Array Substrate (TFT array substrate) and the Color Filter (CF). The light of backlight module is refracted to generate images by applying driving voltages to the two substrates for controlling the rotations of the liquid crystal molecules.
With the development of Low Temperature Poly-Silicon (LTPS) semiconductor thin film transistor, and because the LTPS semiconductor itself has the property of ultra-high carrier mobility, and thus the peripheral circuit around the panel also became the focus that the industry pays lots of attentions.
Please refer to FIG. 1 which is a structure diagram of a liquid crystal display panel according to prior art, comprising an Active Area (AA) 100′, a GOA (Gate Driver on Array) circuit 200′, a Fanout wiring 300′, a demultiplexer (Demux) 400′, a Wire On Array (WOA) 500′, an Integrated Circuit (IC) 600′, a Flexible Printed Circuit (FPC) 700′ and an Array Test circuit 800′. The active area 100′ is employed for the display of pixels, and N is set to be a positive integer. The active area 100′ comprises 4N data lines which are mutually parallel, sequentially aligned and employed to charge the pixels. The arbitrary 4 adjacent data lines in the 4N data lines are one unit to be tested. The four data lines of each unit to be tested are respectively defined to be the first, the second, the third and the fourth data lines D1′, D2′, D3′, D4′. The data lines in the array test circuit 800′ and the active area 100′ are electrically coupled, and employed to perform test to the electrical properties of the array substrate after the manufacture of the array substrate is completed.
Please refer to FIG. 2, which is a circuit diagram of an array test circuit of the liquid crystal display panel shown in FIG. 1, and the array test circuit 800′ comprises N array test circuit units which are paratactic, and each array test circuit unit corresponds to the units to be tested in one active area 100′; each array test circuit comprises, a first thin film transistor T1′, a second thin film transistor T2′, a third thin film transistor T3′, a fourth thin film transistor T4′, a fifth thin film transistor T5′, a sixth thin film transistor T6′, a seventh thin film transistor T7′ and an eighth thin film transistor T8′; gates of the first, the second, the third and the fourth thin film transistors T1′, T2′, T3′, T4′ respectively receive the first, the second, the third and the fourth test clock signals ACK1′, ACK2′, ACK3′, ACK4′, and all sources receive the test data signals Data′, and drains are electrically coupled to the first, the second the third and the fourth nodes A′, B′, C′, D′, respectively; all gates of the fifth, the sixth, the seventh and the eighth thin film transistors T5′, T6′, T7′, T8′ receive the test control signal ATEN′, and sources are electrically coupled to the first, the second the third and the fourth nodes A′, B′, C′, D′, respectively, and drains are electrically coupled to the first, the second the third and the fourth data lines D1′, D2′, D3′, D4′ in the corresponding unit to be tested, respectively.
Please refer to FIG. 3, which is a sequence diagram of the array test circuit of the liquid crystal display panel shown in FIG. 2. As performing the array test, the test control signal ATEN′ is high voltage level to activate the fifth, the sixth, the seventh and the eighth thin film transistors T5′, T6′, T7′, T8′, and the first, the second, the third and the fourth test clock signals ACK1′, ACK2′, ACK3′, ACK4′ sequentially provide high voltage level to sequentially activate the first, the second, the third and the fourth thin film transistors T1′, T2′, T3′, T4′, and the changed data signals Data are respectively inputted to the first, the second, the third and the fourth data lines D1′, D2′, D3′, D4′, and after the corresponding test clock signals ACK1′, ACK2′, ACK3′, ACK4′ are converted to be low voltage levels and keep stable, and then until the next time that the corresponding test clock signal provides high voltage level, the test data signal Data′ is written to the corresponding data line, again. As the array test is accomplished and the liquid crystal display performs the normal display, the test control signal ATEN′ is low voltage level, and the data lines D1′, D2′, D3′, D4′ are provided with data signals by the control IC 600′. Then, the voltage levels of the first, the second, the third and the fourth nodes A′, D′, C′, D′ are in the unknown state to make the voltage differences Vgs of the gates and the sources of the fifth, the sixth, the seventh and the eighth thin film transistors T5′, T6′, T7′, T8′ generate floating to lead to the nonuniform leakages on the different data lines. Thus, the image display in the active area 100′ is nonuniform and the product quality descends.